| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| u0|rst_controller|alt_rst_req_sync_uq1 |
2 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|rst_controller |
33 |
31 |
0 |
31 |
2 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_4|the_altsyncram|auto_generated |
100 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_4 |
106 |
0 |
2 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_3|the_altsyncram|auto_generated |
100 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_3 |
106 |
0 |
2 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_2|the_altsyncram|auto_generated |
100 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_2 |
106 |
0 |
2 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_1|the_altsyncram|auto_generated |
100 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_1 |
106 |
0 |
2 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0|the_altsyncram|auto_generated |
100 |
0 |
0 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0|onchip_memory2_0 |
106 |
0 |
2 |
0 |
64 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u0 |
502 |
161 |
0 |
161 |
320 |
161 |
161 |
161 |
0 |
0 |
0 |
0 |
0 |